1. Field of the Invention
The present invention relates to a random number test circuit.
2. Related Art
Conventionally, there are statistical random number test methods. However, they need a large number of data (20000 bits or more). In addition, they need a large-scale program to implement test items. Therefore, the scale of the random number test circuit becomes large, and test is conducted in a factory at the time of shipping only once. In small-sized information terminals which frequently use random numbers, a small-sized and simple random number test circuit is needed.
On the other hand, there is a self-test random number generation circuit having a random number test circuit incorporated in a chip (see, for example, JP-A 2004-310314 (KOKAI)).
The random number test circuit described in JP-A 2004-310314 (KOKAI) adopts FIPS-140-2 as its test method. As shown in FIG. 10 of JP-A 2004-310314 (KOKAI), the random number test circuit includes a serial physical random number generator 201, a monobit test circuit 202, a poker test circuit 203, a runs test circuit 204 and a long runs test circuit 205 connected to an output of the serial physical random number generator 201 and obtained by implementing test methods of four kinds included in FIPS-140-2 as circuits, and a selector 206 which retains results of tests conducted by the monobit test circuit 202, the poker test circuit 203, the runs test circuit 204 and the long runs test circuit 205 and makes a synthetic decision.
First, serial random numbers output from the serial physical random number generator 201 are coupled to inputs of the monobit test circuit 202, the poker test circuit 203, the runs test circuit 204 and the long runs test circuit 205. Data of 20000 bits are needed for the test. Each of the monobit test circuit 202, the poker test circuit 203, the runs test circuit 204 and the long runs test circuit 205 includes a control circuit, a counter, a comparison circuit and a comparator. Results of tests respectively conducted by the monobit test circuit 202, the poker test circuit 203, the runs test circuit 204 and the long runs test circuit 205 are held in the selector 206. The synthetic decision is output when decision results are success in all of the test methods of the four kinds.
In the test according to the FIPS-140-2, however, the number of data required for the test is very large as many as 20000 bits. An enormous hold circuit is needed to hold the 20000-bit data. In addition, the test methods of four kinds are needed for each cycle of operation required for the test. Each test method requires 20000-bit data. This results in a problem that the circuit scale becomes very large.
The essence of the problem is that if a mathematical test method which is not restricted to the FIPS-140-2 is implemented as a circuit as it is, the area of the circuit becomes enormous. Therefore, it is demanded to reduce the area of the circuit remarkably in order to mount the random number test circuit on a small-sized circuit such as an IC card.